--
-- VHDL Architecture vga_lib.pixel_counter.arch
--
-- Created:
--          by - andax656.student (southfork-12.edu.isy.liu.se)
--          at - 10:21:13 10/05/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY pixel_counter IS
   PORT( 
      fpga_reset_n : IN     std_logic;
      fpga_clk     : IN     std_logic;
      vga_clk      : IN     std_logic;
      pcnt         : BUFFER integer RANGE 0 TO 794
   );

-- Declarations

END pixel_counter ;

-- Genererar pcnt
ARCHITECTURE arch OF pixel_counter IS
BEGIN
  process(fpga_clk)
  begin
    if rising_edge(fpga_clk) then
      
      if fpga_reset_n = '0' then
        pcnt <= 0;
      
      elsif vga_clk = '1' then     
        if pcnt = 793 then
          pcnt <= 0;
        else
          pcnt <= pcnt + 1;   
        end if;
        
      end if;
    end if;
  end process;
END ARCHITECTURE arch;

